搜索资源列表
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
Logicos
- Is a Simple andOr, xor, sr circuit on Verilog and his testBench
UART
- UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
Test
- verilog语言编写的分频程序及其testbench测试文件。fpga开发入门的好例子。-verilog divide written test procedures and testbench files. fpga development of entry-a good example.
verilogtestbench
- 关于verilog的testbench资料文档，通过文档可以更好的了解verilog的testbench的写法。-The testbench verilog information about the document, through a better understanding of the document to the testbench verilog is written.
doublefloat_RAM
- 使用verilog编写的一个双浮点RAM，支持对字、字节、半字、双字的读写，包含testbench和wave.do文件-Use verilog to implement a double float RAM, supporting the read and write of halfword,byte,word,double word. It includes the testbench and wave.do
fibonacci_matlab_verilog
- 使用Matlab和Verilog实现fibonacci序列，包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
Writing-Testbenches--
- 介绍如何使用system verilog搭建testbench。-introduce how to use the system verilog to writing testbench
eprom
- Verilog编写的eprom仿真模型，包括testbench文件和测试用bin文件-Write eprom Verilog simulation model, including the testbench file and bin file for testing
hand_shake
- 握手程序，可以完美实现跨时钟域的数据传输-handshake and testbench，verilog HDL
74serie-code
- 74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
testbench_P_verilog
- 怎样编写testbench verilog-how to write testbench verilog
rgb2yuv
- 在Altera的开发环境上，用Verilog语言实现的RGB转YUV，附有Testbench-In Altera s development environment, using Verilog language of RGB to YUV, with a Testbench
divide
- divide模块，实现除法功能。该module是用Verilog编写的，压缩包里包括了设计程序以及测试程序（testbench）。-divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
verilogCRC32
- 32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码-The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench
fifo
- 利用verilog来实现fifo的读写，并有testbench程序。-fifo verilog
I2C_verilogcode
- verilog的i2c代码，含仿真环境，测试testbench等-i2c code use verilog，with verification testbench
My_DES3
- a triple-DES (Data Encryption Standard) hardware descr iption in verilog-HDL with testbench
fre
- verilog hdl 开发的频率计，运行环境 DE2-115开发板，内有modelsim仿真用的testbench。RTL级代码-verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code
matrix-keyboard-
- 矩阵键盘控制的FPGA，verilog语言实现，包括rtl，ucf,以及testbench的详尽代码-Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench